Conventional wide range programmable delay cells consume a relative large amount of silicon die area. In most conventional delay lines, a delay chain is made of a number of delay elements. Each delay element provides a relatively equal delay, which results in a fairly large delay chain with respect to silicon area.
Designers normally try to minimize the silicon area by carefully laying out the cell and trying to compact the logic as much as possible. In addition, careful layout techniques are used to balance out each step so that every delay step produces similar delay value.
Implementing a conventional delay cell takes design effort when trying to match the delay for each delay step as well while trying to minimize die size.
It would be desirable to implement a delay cell that is easy to implement and has efficient die usage.